1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device, in particular, a silicon carbide semiconductor device having a drift region.
2. Description of the Background Art
Regarding a Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is a pervasive power semiconductor device, a main determination factor for breakdown voltage is the upper limit of electric field strength with which a drift layer serving as a breakdown voltage holding region can withstand. Such a drift layer formed of Si can be broken at a portion fed with an electric field of approximately 0.3 MV/cm or more. Hence, it is necessary to suppress the electric field strength to less than a predetermined value in the whole of the drift layer of the MOSFET. The simplest method to suppress is to decrease an impurity concentration of the drift layer. However, with this method, the on-resistance of the MOSFET becomes large, disadvantageously. In other words, there is a trade-off relation between the on-resistance and the breakdown voltage.
Japanese Patent Laying-Open No. 9-191109 describes such a trade-off relation between the on-resistance and the breakdown voltage in a typical Si MOSFET while considering a theoretical limit resulting from a property value of Si. In order to overcome this trade off, it is disclosed to add a lower p type buried layer and an upper p type buried layer in an n base layer disposed on an n type substrate disposed on a drain electrode. By the lower p type buried layer and the upper buried layer, the n base layer is divided into a lower stage, a middle stage, and an upper stage, each of which has the same thickness. According to one embodiment described in this patent publication, when an applied voltage reaches 200 V, punch through first occurs in the upper stage. Further, when the applied voltage reaches 400 V, punch through occurs in the middle stage. Furthermore, when the applied voltage reaches 600 V, punch through occurs in the lower stage. The stages in each of which the punch through has occurred hold equal voltages and the maximum electric field of each stage is maintained to be equal to or less than a limit electric field strength.
In order to further improve the above-described trade off, in recent years, it has been actively discussed to use SiC (silicon carbide) instead of Si. Unlike Si, SiC is a material capable of sufficiently withstanding an electric field strength of not less than 0.4 MV/cm.
A problem arising under application of such a high electric field is breakdown resulting from concentrated electric fields at a specific location in the MOSFET structure. For example, in the case of a trench type MOSFET, a main determination factor for breakdown voltage is a breakdown phenomenon of a gate insulating film. The breakdown phenomenon occurs at a bottom portion of the trench, in particular, a corner portion thereof, due to concentrated electric fields in the gate insulating film. Thus, the determination factor for breakdown voltage in the Si semiconductor device and the determination factor for breakdown voltage in the SiC semiconductor device are different from each other. Hence, if the technique of the above-described patent publication, which presumably assumes use of Si, is simply applied to improve the breakdown voltage of the SiC semiconductor device, the breakdown voltage cannot be improved by sufficiently using advantages in physical properties of SiC.